Design Embedded DRAM in Conventional Digital CMOS Process

If an embedded DRAM (eDRAM) block is to be integrated into a System-on-Chip (SoC), a fundamental trade-off arises between cell density and data retention time. Identifying the optimal balance between these two parameters is essential for achieving the desired performance, area efficiency, and reliability. In the following article, this trade-off is analyzed and discussed in detail.