MOSFET Small-Signal Characteristics

In this article, we extract the small-signal characteristics of MOSFETs using open-source and free available PDKs and CAD tools. The analysis is carried out using the SkyWater sky130 PDK, Xschem as the schematic capture tool, and Ngspice as the circuit simulator.

All tools (Xschem, Ngfspice, and sky130 PDK) must be installed properly on a Linux system. In this work, Ubuntu running under WSL is used. The installation procedure is discussed in a separate article.

The reader is assumed to have a basic understanding of MOSFET device physics and the fundamentals of MOSFET operation. Figure 1 illustrates the structure and symbols of NMOS and PMOS devices. In integrated-circuit design, each MOSFET has four terminals: gate (G), source (S), drain (D), and bulk (B). Modern CMOS technologies typically employ a p-type substrate; therefore, the bulk of all NMOS devices (except native devices) is tied to the substrate, i.e., GND or VSS. In contrast, PMOS devices are fabricated in isolated wells, allowing their bulks to be biased independently.

Figure 1: (a) structure of NMOS and PMOS, (b) symbols (from [1])

Operation regions:

A MOSFET behaves as a switch (ON or OFF) in digital design, but in analog design it operates in one of three regions:

  • Cut-off (OFF):           VGS < VTH and VGD < 0
  • Saturation:                 VGS > VTH and VGD < VTH
  • Triode (ON):              VGS > VTH and VGD > VTH

Note that the transition between these regions is smooth, especially near the threshold voltage. 

Voltage – Current Characteristics:

To explain MOSFET operation, we review the V–I equations of an NMOS transistor. PMOS equations follow the same form.

Triode region (ON):

ID=μnCoxWL[(VGSVTH)VDS12VDS2](1)I_D=\mu_nC_{ox}\frac{W}{L}\left[\left(V_{GS}-V_{TH}\right)V_{DS}-\frac{1}{2}V_{DS}^2\right] \qquad (1)

For VDS << 2(VGS – VTH):

IDμnCoxWL(VGSVTH)VDS(2)I_D\approx\mu_nC_{ox}\frac{W}{L}\left(V_{GS}-V_{TH}\right)V_{DS} \qquad (2)

Saturation region:

Including channel length modulation,

ID=12μnCoxWL(VGSVTH)2(1+λ VDS)(3)I_D=\frac{1}{2}\mu_nC_{ox}\frac{W}{L}\left(V_{GS}-V_{TH}\right)^2(1+\lambda\ V_{DS}) \qquad (3)

The parameter λ is the channel-length modulation coefficient, which decreases with increasing channel length:

λ1L(4)\lambda\propto\frac{1}{L} \qquad (4)

Second-order effects:

Body effect: Increasing the source-to-bulk voltage raises the threshold voltage:

VTH=VTH0+γ(2ΦF+VSB|2ΦF|)(5)V_{TH}=V_{TH0}+\gamma\left(\sqrt{2\Phi_F+V_{SB}}-\sqrt{\left|2\Phi_F\right|}\right) \qquad (5)
γ=2qϵsiNsubCox0.3 to 0.4 (V12)(6)\gamma=\frac{\sqrt{2q\epsilon_{si}N_{sub}}}{C_{ox}}\approx0.3\ to\ 0.4\ \left(V^\frac{1}{2}\right) \qquad (6)
VTH0=ΦMS+2ΦF+QdepCox=VTH for VSB=0(7)V_{TH0}=\Phi_{MS}+2\Phi_F+\frac{Q_{dep}}{C_{ox}}=V_{TH}\ for\ V_{SB}=0 \qquad (7)

Subthreshold (Weak Inversion) : When VGS ≈ VTH, the device enters weak inversion, and the drain current follows:

ID=I0expVGSξVT(8)I_D=I_0\exp{\frac{V_{GS}}{\xi V_T}} \qquad (8)

where I0 is proportional to W/L, and ξ > 1 and VT = kT/q. We say the device operates in weak inversion in contrast with strong inversion.

Small-signal model:

Fig.2 shows the small-signal MOSFET model [1].

Figure 2: (a) Basic MOS small-signal model; (b) channel-length modulation represented by a dependent current source; (c) channel-length modulation represented by a resistor; (d) body effect represented by a dependent current source. [1]

Equations:

In triode region, a MOSFET behaves as a voltage-controlled resistor:

Ron=1μnCoxWL(VGSVTH)(9)R_{on}=\frac{1}{\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH})} \qquad (9)

In saturation, the transconductance is:

gm=IDVGS(10)g_m=\frac{\partial I_D}{\partial V_{GS}} \qquad (10)

Equivalent expressions include:

gm=μnCoxWL(VGSVTH)(11)g_m=\mu_nC_{ox}\frac{W}{L}(V_{GS}-V_{TH}) \qquad (11)
gm=2μnCoxWLID(12)g_m=\sqrt{2\mu_nC_{ox}\frac{W}{L}I_D} \qquad (12)
gm=2IDVGSVTH(13)g_m=\frac{2I_D}{V_{GS}-V_{TH}} \qquad (13)

The output resistance due to channel-length modulation is:

ro=1gds=VDSID=112μnCoxWL(VGSVTH)2×λ(14)r_o=\frac{1}{g_{ds}}=\frac{\partial V_{DS}}{\partial I_D}=\frac{1}{\frac{1}{2}\mu_nC_{ox}\frac{W}{L}\left(V_{GS}-V_{TH}\right)^2\times\lambda} \qquad (14)

For λVDS << 1,

ro=1gds1+λVDSλID1λID(15)r_o=\frac{1}{g_{ds}}\approx\frac{1+\lambda V_{DS}}{\lambda I_D}\approx\frac{1}{\lambda I_D} \qquad (15)

The body-effect transconductance is:

gmb=IDVBS=gmγ22ΦF+VSB=η gm(16)g_{mb}=\frac{\partial I_D}{\partial V_{BS}}=gm\frac{\gamma}{2\sqrt{2\Phi_F+V_{SB}}}=\eta\ g_m \qquad (16)

where η is typically around 0.25

Simulation results:

Long-channel NMOS: The circuit in fig. 3 is used to evaluate the small-signal, low frequency behavior of an NMOS device. Because capacitances are not considered in this section, DC-sweep analysis is employed.

Figure 3: Simple NMOS circuit used for DC-sweep analysis

Here, the W/L is 100u/1.5u, number of gates (fingers) are 10, and the VGS sweep is from 0 to 1.8V. Fig. 4 shows gm and gds of the NMOS versus VGS.

Figure 4(a)
Figure 4(b)

In this circuit, VTH ≈ 560mv. As expected, by increasing VGS, both gm and gds increase. It’s interesting to see the gds – ID relationship as shown in fig. 5. The curve is nearly linear, and according to (15), its slope is corresponds to the channel-length modulation coefficient λ.

Figure 5: gds vs. ID

The intrinsic small-signal gain of a MOSFET is defined as

Av=gmro=gmgds(17)A_v=g_mr_o=\frac{g_m}{g_{ds}} \qquad (17)

Fig. 6 plots the gain vs. VGS.

Figure 6: Intrinsic small-signal low-frequency gain of NMOS with W/L = 100u/1.5u

In this example of long-channel NMOS, the gain peaks at an overdrive voltage of Vov = VGS – VTH ≈ 100 mV.

As Vov (and thus ID) increases, the gain decreases. Below Vov ≈ 80 mV, the device is in weak inversion, and for VGS < VTH, the gain loses its physical meaning.

Short-channel (sub-micron) NMOS: For channel length below 1 um (sub-micron), the MOS device behavior is significantly affected by short-channel and higher-order effects. Figure 7 illustrates how these phenomena alter the small-signal parameters for a device with W/L = 10u/0.15u. Detailed discussion of short-channel devices will be provided in a subsequent article.

Figure 7(a)
Figure 7(b)
Figure 7(c)
Figure 7(d)

[1] Razavi, B., Design of Analog CMOS Integrated Circuits, 2nd ed. New York, NY, USA: McGraw-Hill, 2017.

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